`timescale 1ns / 1ns

module tff (
    input  t,
    input  clk,
    input  rst,
    output reg out
);

    initial begin
        out <= 0;
    end

    always @(posedge clk or negedge rst) begin
        if (rst == 0) begin
            out <= 0;
        end else if (t != 0) begin
            out <= ~out;
        end
    end

endmodule

module Tff_2 (
    input data,
    input clk,
    input rst,
    output q
);

    wire mid;

    tff tff1 (
        .t  (data),
        .clk(clk),
        .rst(rst),
        .out(mid)
    );

    tff tff2 (
        .t  (mid),
        .clk(clk),
        .rst(rst),
        .out(q)
    );

endmodule
